1. Field of the Invention
The invention relates to a digital fractional phase detector, and more particularly, to a digital fractional phase detector for use in a digital frequency synthesizer.
2. Description of the Prior Art
Frequency synthesizers using analog circuit techniques are well known in the art. Conventional RF frequency synthesizer architectures are analog-intensive and generally require a low loop bandwidth to reduce the familiar and well-known reference or compare frequency spurs.
The conventional PLL-based frequency synthesizers generally comprise analog-intensive circuitry that does not work very well in a low voltage constrained high-speed CMOS environment. Such frequency synthesizers do not take advantage of recently developed high-density digital gate technology.
Newer frequency synthesizer architectures have used sigma-delta modulated frequency divider techniques to randomize the above discussed frequency spurs by randomizing the spurious content at the cost of increased noise floor. These techniques have not significantly reduced the undesirable analog content. Other frequency synthesizer architectures have used direct digital synthesis (DDS) techniques that do not work at RF frequencies without a frequency conversion mechanism requiring an analog solution. Further, most previous all-digital PLL architectures rely on an over-sampling clock. Such architectures cannot be used at RF frequencies.
In view of the foregoing, it is highly desirable to have a technique to implement a digitally-intensive frequency synthesizer architecture that is compatible with modern CMOS technology and that has an accurate phase quantization resolution to accommodate wireless applications.
Staszewski et al. in U.S. Pat. No. 6,429,693 describe a digital fractional phase detector using a delay chain to measure fractional delay differences between the significant edge of a VCO output clock and a reference clock by using a time-to-digital converter to express the time difference as a digital word for use by the frequency synthesizer. However, because the VCO output clock and the reference clock are not synchronous signals with respect to each other, quantization resolution and accuracy is not optimal.